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EL7202, EL7212, EL7222
Data Sheet July 3, 2006 FN7282.2
High Speed, Dual Channel Power MOSFET Drivers
The EL7202, EL7212, EL7222 ICs are matched dual-drivers that improve the operation of the industry standard DS0026 clock drivers. The Elantec versions are very high speed drivers capable of delivering peak currents of 2.0 amps into highly capacitive loads. The high speed performance is achieved by means of a proprietary "Turbo-Driver" circuit that speeds up input stages by tapping the wider voltage swing at the output. Improved speed and drive capability are enhanced by matched rise and fall delay times. These matched delays maintain the integrity of input-to-output pulse-widths to reduce timing errors and clock skew problems. This improved performance is accompanied by a 10 fold reduction in supply currents over bipolar drivers, yet without the delay time problems commonly associated with CMOS devices. Dynamic switching losses are minimized with non-overlapped drive techniques.
Features
* Industry standard driver replacement * Improved response times * Matched rise and fall times * Reduced clock skew * Low output impedance * Low input capacitance * High noise immunity * Improved clocking rate * Low supply current * Wide operating voltage range * Pb-Free available (RoHS compliant)
Applications
* Clock/line drivers * CCD Drivers * Ultra-sound transducer drivers * Power MOSFET drivers * Switch mode power supplies * Class D switching amplifiers * Ultrasonic and RF generators * Pulsed circuits
Pinouts
EL7212 (8-PIN PDIP, SO) TOP VIEW EL7222 (8-PIN PDIP, SO) TOP VIEW
INVERTING DRIVERS
COMPLEMENTARY DRIVERS
EL7202 (8-PIN PDIP, SO) TOP VIEW
NON-INVERTING DRIVERS Manufactured under U.S. Patent Nos. 5,334,883, #5,341,047
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003, 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7202, EL7212, EL7222
Ordering Information
Part Number EL7202CN EL7202CS EL7202CS-T7 EL7202CS-T13 EL7202CSZ (See Note) EL7202CSZ-T7 (See Note) EL7202CSZ-T13 (See Note) EL7212CN EL7212CNZ EL7212CS EL7212CS-T7 EL7212CS-T13 EL7212CSZ (See Note) EL7212CSZ-T7 (See Note) EL7212CSZ-T13 (See Note) EL7222CN EL7222CS EL7222CS-T7 EL7222CS-T13 EL7222CSZ (See Note) EL7222CSZ-T7 (See Note) EL7222CSZ-T13 (See Note) PART MARKING EL7202CN 7202CS 7202CS 7202CS 7202CSZ 7202CSZ 7202CSZ EL7212CN EL7212CN Z 7212CS 7212CS 7212CS 7212CSZ 7212CSZ 7212CSZ EL7222CN 7222CS 7222CS 7222CS 7222CSZ 7222CSZ 7222CSZ TAPE & REEL 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" 7" 13" PACKAGE 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld PDIP* (Pb-free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld PDIP 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) 8 Ld SOIC (Pb-free) PKG. DWG. # MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0031 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0031 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
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FN7282.2 July 3, 2006
EL7202, EL7212, EL7222
Absolute Maximum Ratings (TA = 25C)
Supply (V+ to Gnd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V above V+ Combined Peak Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . .4A Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125C Power Dissipation SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .570mW PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1050mW
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications parameter INPUT VIH IIH VIL IIL VHVS OUTPUT ROH ROL IPK IDC POWER SUPPLY IS
TA = 25C, V = 15V unless otherwise specified Description Test Conditions Min Typ Max Units
Logic "1" Input Voltage Logic "1" Input Current Logic "0" Input Voltage Logic "0" Input Current Input Hysteresis @0V @V+
2.4 0.1 10 0.8 0.1 0.3 10
V A V A V
Pull-Up Resistance Pull-Down Resistance Peak Output Current Continuous Output Current
IOUT = -100mA IOUT = +100mA Source Sink Source/Sink 100
3 4 2 2
6 6
A mA
Power Supply Current
Inputs High/EL7202 Inputs High/EL7212 Inputs High/EL7222 4.5
4.5 1 2.5
7.5 2.5 5.0 15
mA V
VS
Operating Voltage TA = 25C, V = 15V unless otherwise specified Description Test Conditions
AC Electrical Specifications parameter SWITCHING CHARACTERISTICS tR tF tD1 tD2 Rise Time Fall Time
Min
Typ
Max
Units
CL = 500pF CL = 1000pF CL = 500pF CL = 1000pF See Timing Table See Timing Table
7.5 10 10 13 18 20
ns 20 ns 20 25 25 ns ns
Turn-On Delay Time Turn-Off Delay Time
3
FN7282.2 July 3, 2006
EL7202, EL7212, EL7222 Timing Table
Standard Test Configuration
Simplified Schematic
4
FN7282.2 July 3, 2006
EL7202, EL7212, EL7222 Typical Performance Curves
MAX POWER/DERATING CURVES SWITCH THRESHOLD vs SUPPLY VOLTAGE
INPUT CURRENT vs VOLTAGE
PEAK DRIVE vs SUPPLY VOLTAGE
QUIESCENT SUPPLY CURRENT
"ON" RESISTANCE vs SUPPLY VOLTAGE
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FN7282.2 July 3, 2006
EL7202, EL7212, EL7222 Typical Performance Curves
(Continued)
AVERAGE SUPPLY CURRENT vs CAPACITIVE LOAD
AVERAGE SUPPLY CURRENT vs VOLTAGE AND FREQUENCY
RISE/FALL TIME vs LOAD
RISE/FALL TIME vs SUPPLY VOLTAGE
PROPAGATION DELAY vs SUPPLY VOLTAGE
RISE/FALL TIME vs TEMPERATURE
DELAY vs TEMPERATURE
6
FN7282.2 July 3, 2006
EL7202, EL7212, EL7222 EL7212 Macro Model
**** EL7212 model **** * input * | gnd * | | Vsupply * | | | Vout .subckt M7212 2 3 6 7 V1 12 3 1.6 R1 13 15 1k R2 14 15 5k R5 11 12 100 C1 15 3 43.3 pF D1 14 13 dmod X1 13 11 2 3 comp1 X2 16 12 15 3 comp1 sp 6 7 16 3 spmod sn 7 3 16 3 snmod g1 11 0 13 0 938 .model dmod d .model spmod vswitch ron3 roff2meg von1 voff1.5 .model snmod vswitch ron4 roff2meg von3 voff2 .ends M7212 .subckt comp1 out inp inm vss e1 out vss table { (v(inp) v(inm))* 5000} (0,0) (3.2,3.2) Rout out vss 10meg Rinp inp vss 10meg Rinm inm vss 10meg .ends comp1
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FN7282.2 July 3, 2006
EL7202, EL7212, EL7222 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. L 2/01
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FN7282.2 July 3, 2006
EL7202, EL7212, EL7222 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031 PLASTIC DUAL-IN-LINE PACKAGE SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. B 2/99 NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN7282.2 July 3, 2006

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